Traditional processor architectures have inherent limitations in fulfilling the high-performance needs of modern applications. This necessitated the development of domain-specific architectures and hardware accelerators. After a decade of development, RISC-V is now evolving as the preferred instruction-set-architecture for a wide range of modern processing workloads, especially in embedded, mobile and machine learning systems. And yet, not many outside of the hardware computing community are discussing this major technological evolution.
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What is RISC-V?
To understand RISC-V, we need to first understand ISA, CISC and RISC. Put simply, an Instruction Set Architecture (ISA) is an abstract model of a computer that serves as an interface between the hardware and the software. It defines the behavior of the machine code without depending on specific machine implementations. It defines the instructions for arithmetic & logic operations, control flow operations, data handling, memory operations, etc. A single ISA may have different implementations.
Two major types of ISAs are Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC). In general, RISC is considered to be an improvement over the older CISC. RISC is based on simple, fixed-length and single clock-cycle instructions. CISC, on the other hand, involves complex and variable-length instructions, including those with more than one clock-cycle. Moreover, CISC is more hardware-centric where the transistor circuitry does a lot of the heavy lifting. On the other hand, software (compilers and code) play a bigger role in RISC, thus making it more software-centric. Finally, RISC is significantly more RAM-consuming vis-à-vis CISC.
Examples of CISC-based microprocessors include the older generations of Intel x86, DEC VAX, Motorola 68K and PDP-11. On the other hand, most modern microprocessors, such as ARM, AVR, Microchip PIC, MIPS, OpenRISC, PowerPC, SPARC and SuperH are based on the RISC architecture, at least to some extent. Over the years, both CISC and RISC have borrowed elements from each other.
The basic idea of RISC was to enable microprocessors to operate with fewer cycles per instruction, thus enabling high performance and faster computing. However, conventional RISC (as well as CISC) suffer from certain critical problems, e.g., high complexity, IP-related restrictions, etc. This necessitated the development of a commercial-grade, open-source and simplified instruction set that could not only offer fast performance, but could also be easily customized for specialized computing workloads. The idea of RISC-V was born and development started at the University of California, Berkeley in 2010. Apart from representing open architecture, RISC-V aims to enable support for a wide range of devices ranging from embedded servers to cloud-based servers, and from micro-controllers to supercomputers.
The Increasing Significance of RISC-V
For most of computing history, ISAs have been controlled by a handful of companies, such as Intel and ARM. RISC-V is a major step towards breaking this hold, thus opening up the competitive space and the scope for more innovations. Moreover, the application of RISC-V is geared towards developing complex applications that range from embedded and mobile devices to large-scale high performance computing (HPC) servers. Most vector extensions of RISC-V are considered suitable for complex workloads that involve high data parallelism (e.g., stream processing and machine learning) and low-energy processing (e.g. edge computing.)
An important aspect of RISC-V is that it is designed as a base architecture for simple workloads that is easily extendable to deliver more complex workloads. The base ISA provides default support for integer addition/subtraction but not for multiplication/division. This is an efficient approach because unlike addition/subtraction, multiplication/division are relatively expensive operations and may not be needed in all types of processing operations. As a result, technological complexity and processing costs are reduced by including only the most common and less expensive operations in the default base setup.
Complex workloads (e.g., atomic memory operations, floating-point mathematics, privileged execution implementations, etc.) are fulfilled by deploying suitable extensions on this base ISA. This enables chips to be developed and optimized through a modular structure on which individual extensions are added based on specific computing requirements. In general, traditional RISC chips are loaded with pre-packaged capabilities that may not be even needed by many applications, thus causing unnecessary energy consumption and performance issues. Hence, the RISC-V approach is a major improvement.
Current Adoption
RISC-V is supported by a number of language compilers today, including the GNU Compiler Collection (GCC)and 32-bit/64-bit Linux distributions. Many open-source processors, such as include Ariane, lowRisc, Rocket-Chip and SHAKTI, are now built around the RISC-V architecture. SiFive, which is backed by industry leaders like Qualcomm, Samsung and Intel, is amongst the well known names today.
Some of the core implementations of established companies are also centered around the RISC-V ISA. Examples include Bluespec’s Piccolo/Flute, MicroChip’s PolarFire, Samsung’s Exynos and Western Digital’s SweRV Core. A new RISC-V processor called Snitch reportedly achieves up to 3.5x energy efficiency and 6x speed as compared to the other benchmark processors. Earlier this year, Esperanto launched their AI accelerator with over 1000 RISC-V specialized cores. More recently, Imagination announced the Catapult family of RISC-V cores that paves the way for their heterogeneous computing roadmap.
Strong industry partnerships are now formed to design and develop the next-generation of RISC-V SoCs (system-on-a-chip). For instance, in April 2021, Samsung Foundry and SiFive announced their partnership to accelerate the development of AI SoCs by leveraging SiFive’s RISC-V processors and Samsung Foundry’s technical infrastructure. In Dec 2021, the RISC-V International ratified new vector, scalar cryptography and hypervisor specifications to accelerate global adoption across a variety of segments that includes autonomous vehicles, data centers and the Internet of Things.
Challenges & Future Direction
The challenges related to RISC-V are broadly around three areas – development complexities, security concerns and tooling limitations. The lack of a matured ecosystem around RISC-V often leads to computational complexities and poor software implementations. For instance, despite all the energy efficiencies and fast performance, several RISC-V processors (e.g., Snitch) are quite complex to program as compared to conventional processors. Moreover, the lack of robust performance monitoring tools make it difficult to monitor and triage execution-time bottlenecks. Some critics also opine that RISC-V does not really offer any major innovations beyond applying the RISC guidelines towards building an open-source ISA.
Furthermore, the verification and compliance management processes for RISC-V development are still in formative stages. Considering that verification represents a major chunk of chip development efforts, it is a major challenge today. Most of the tooling (e.g., conformance testing platforms, stimulus generators, virtual simulators, etc.) are not yet mature. Additionally, RISC-V implementations are generally customized and involve domain-specific programming. These factors also pose several challenges in developing standardized frameworks and enabling reusability for many modern use cases.
The security foundations of RISC-V are still evolving. The detection and remediation of complex vulnerabilities (e.g., covert/side channels, electromagnetic fault injection, hardware trojans, logic-locking attacks, physical access attacks and RTL bugs) are current areas of research. Other areas of research include developing energy-efficient cryptographic engines & program obfuscators; achieving efficiencies in memory encryption, authentication & isolation; and enabling the portability of existing security frameworks on to the RISC-V ecosystem.
Artificial Intelligence is one of the most important application areas for RISC-V. Specialized chips can be designed, developed and optimized to address the computation needs of complex tasks like action recognition, emotion analysis, object detection & segmentation, natural language generation, and others. The Compute Unified Device Architecture (CUDA) is another example. While CUDA is currently the most preferred platform for computing on general-purpose graphics processing units (GPGPUs), its source code can be compiled and executed only on NVIDIA’s products. This is a major obstacle for AI democratisation, and may also lead to a case of industry monopoly. The solution lies in developing capabilities for compiling and executing the CUDA code on RISC-V GPU architectures. This subject forms a major area of research today.
Closing Comments
The RISC-V revolution is likely to fuel massive disruptions in the semiconductor industry. It has the potential to break the long-standing oligopoly of a handful of companies, and the stronghold of a few countries. As RISC-V becomes a stronger alternative to x86 and ARM, it also establishes a robust, open architectural framework that will fuel more globalized, more collaborative, more transformative innovations.
For instance, China has already started developing the larger ecosystems around RISC-V in order to break the United States’ dominance. Alibaba has ported the RISC-V ISA to the Android OS and T-Head, it’s subsidiary, has open-sourced their XuanTie RISC-V cores. Other Chinese companies are in the process of building RISC-V based smartphones, wearables, etc. Similarly, the European Processor Initiative (EPI) aims to establish the Europe Union’s independence in high-performance computing. As part of that program, it is working on an ambitious RISC-V based Exascale Computing Machine.
The future lies in chip specialization.
High degrees of efficiencies can be achieved by deploying domain-based or application-based chips instead of the generic ones, especially in resource-intensive or long-running tasks. The global shortage of chips that we face today, coupled with the massive disruptions caused by Covid, will expedite many of the changes discussed in this paper. In general, companies are far more open to exploring RISC-V as the future industry standard. For example, it is widely speculated that Apple is considering a shift from ARM towards RISC-V for the future generations of their chips. Considering Apple’s traditional relationship with ARM, this singular event will provide a significant boost to the RISC-V revolution.
The next three to five years will fundamentally transform system architecture and the computing world. And this upcoming disruption needs more attention from the global technology community today.